--- ../../../BAT32G137.h	2020-04-10 18:50:09.626200600 +0800
+++ BAT32G137.h	2020-04-10 19:03:43.256219600 +0800
@@ -66,13 +66,25 @@
   INTP4_IRQn                =   5,              /*!< 5  INTP4 External interrupt request input is valid                        */
   INTP5_IRQn                =   6,              /*!< 6  INTP5 External interrupt request input is valid                        */
   ST2_IRQn                  =   7,              /*!< 7  UART2 transmission transfer end or buffer empty                        */
+  SPI20_IRQn                =   7,              /*!< 7  SPI20 transfer end or buffer empty                                     */
+  IIC20_IRQn                =   7,              /*!< 7  IIC20 transfer end                                                     */
   SR2_IRQn                  =   8,              /*!< 8  UART2 rerception transfer                                              */
+  SPI21_IRQn                =   8,              /*!< 8  SPI21 transfer end or buffer empty                                     */
+  IIC21_IRQn                =   8,              /*!< 8  IIC21 transfer end                                                     */
   SRE2_IRQn                 =   9,              /*!< 9  UART2 rerception communication error occurrence                        */
   ST0_IRQn                  =  10,              /*!< 10 UART0 transmission transfer end or buffer empty                        */
+  SPI00_IRQn                =  10,              /*!< 10 SPI00 transfer end or buffer empty                                     */
+  IIC00_IRQn                =  10,              /*!< 10 IIC00 transfer end                                                     */
   SR0_IRQn                  =  11,              /*!< 11 UART0 rerception transfer                                              */
+  SPI01_IRQn                =  11,              /*!< 11 SPI01 transfer end or buffer empty                                     */
+  IIC01_IRQn                =  11,              /*!< 11 IIC01 transfer end                                                     */
   SRE0_IRQn                 =  12,              /*!< 12 UART0 rerception communication error occurrence                        */
   ST1_IRQn                  =  13,              /*!< 13 UART1 transmission transfer end or buffer empty                        */
+  SPI10_IRQn                =  13,              /*!< 13 SPI10 transfer end or buffer empty                                     */
+  IIC10_IRQn                =  13,              /*!< 13 IIC10 transfer end                                                     */
   SR1_IRQn                  =  14,              /*!< 14 UART1 rerception transfer                                              */
+  SPI11_IRQn                =  14,              /*!< 14 SPI11 transfer end or buffer empty                                     */
+  IIC11_IRQn                =  14,              /*!< 14 IIC11 transfer end                                                     */
   SRE1_IRQn                 =  15,              /*!< 15 UART1 rerception communication error occurrence                        */
   IICA_IRQn                 =  16,              /*!< 16 IICA interrupt request                                                 */
   TM00_IRQn                 =  17,              /*!< 17 TM4 channel 0 interrupt request                                        */
@@ -112,9 +124,11 @@
 
 /* ==========================  Configuration of the ARM Cortex-M0+ Processor and Core Peripherals  =========================== */
 #define __CM0PLUS_REV                 0x0001U   /*!< CM0PLUS Core Revision                                                     */
+#define __MPU_PRESENT             	   1        /*!< Set to 1 if MPU is present                                                */
+#define __VTOR_PRESENT                 1        /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
 #define __NVIC_PRIO_BITS               2        /*!< Number of Bits used for Priority Levels                                   */
 #define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
-#define __VTOR_PRESENT                 1        /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
+#define __FPU_PRESENT             	   0        /*!< Set to 1 if FPU is present                                                */
 
 
 /** @} */ /* End of group Configuration_of_CMSIS */
@@ -1228,15 +1242,15 @@
 
 
 /* =========================================================================================================================== */
-/* ================                                         CANMSG00                                          ================ */
+/* ================                                         CANMSG                                            ================ */
 /* =========================================================================================================================== */
 
 
 /**
-  * @brief CAN Controller Message 00 (CANMSG00)
+  * @brief CAN Controller Message (CANMSG)
   */
 
-typedef struct {                                /*!< (@ 0x40045500) CANMSG00 Structure                                         */
+typedef struct {                                /*!< (@ 0x40045500) CANMSG Structure                                           */
   
   union {
     __IOM uint16_t C0MDB01;                     /*!< (@ 0x00000000) CAN0 message data byte 01 register                         */
@@ -1278,7 +1292,7 @@
   __IOM uint16_t  C0MIDL;                       /*!< (@ 0x0000000A) CAN0 message ID register                                   */
   __IOM uint16_t  C0MIDH;                       /*!< (@ 0x0000000C) CAN0 message ID register                                   */
   __IOM uint16_t  C0MCTRL;                      /*!< (@ 0x0000000E) CAN0 message control register                              */
-} CANMSG00_Type;                                /*!< Size = 16 (0x10)                                                          */
+} CANMSG_Type;                                  /*!< Size = 16 (0x10)                                                          */
 
 
 
@@ -1426,22 +1440,22 @@
 #define CRC                         ((CRC_Type*)               CRC_BASE)
 #define DBG                         ((DBG_Type*)               DBG_BASE)
 #define CAN                         ((CAN_Type*)               CAN_BASE)
-#define CANMSG00                    ((CANMSG00_Type*)          CANMSG00_BASE)
-#define CANMSG01                    ((CANMSG00_Type*)          CANMSG01_BASE)
-#define CANMSG02                    ((CANMSG00_Type*)          CANMSG02_BASE)
-#define CANMSG03                    ((CANMSG00_Type*)          CANMSG03_BASE)
-#define CANMSG04                    ((CANMSG00_Type*)          CANMSG04_BASE)
-#define CANMSG05                    ((CANMSG00_Type*)          CANMSG05_BASE)
-#define CANMSG06                    ((CANMSG00_Type*)          CANMSG06_BASE)
-#define CANMSG07                    ((CANMSG00_Type*)          CANMSG07_BASE)
-#define CANMSG08                    ((CANMSG00_Type*)          CANMSG08_BASE)
-#define CANMSG09                    ((CANMSG00_Type*)          CANMSG09_BASE)
-#define CANMSG10                    ((CANMSG00_Type*)          CANMSG10_BASE)
-#define CANMSG11                    ((CANMSG00_Type*)          CANMSG11_BASE)
-#define CANMSG12                    ((CANMSG00_Type*)          CANMSG12_BASE)
-#define CANMSG13                    ((CANMSG00_Type*)          CANMSG13_BASE)
-#define CANMSG14                    ((CANMSG00_Type*)          CANMSG14_BASE)
-#define CANMSG15                    ((CANMSG00_Type*)          CANMSG15_BASE)
+#define CANMSG00                    ((CANMSG_Type*)            CANMSG00_BASE)
+#define CANMSG01                    ((CANMSG_Type*)            CANMSG01_BASE)
+#define CANMSG02                    ((CANMSG_Type*)            CANMSG02_BASE)
+#define CANMSG03                    ((CANMSG_Type*)            CANMSG03_BASE)
+#define CANMSG04                    ((CANMSG_Type*)            CANMSG04_BASE)
+#define CANMSG05                    ((CANMSG_Type*)            CANMSG05_BASE)
+#define CANMSG06                    ((CANMSG_Type*)            CANMSG06_BASE)
+#define CANMSG07                    ((CANMSG_Type*)            CANMSG07_BASE)
+#define CANMSG08                    ((CANMSG_Type*)            CANMSG08_BASE)
+#define CANMSG09                    ((CANMSG_Type*)            CANMSG09_BASE)
+#define CANMSG10                    ((CANMSG_Type*)            CANMSG10_BASE)
+#define CANMSG11                    ((CANMSG_Type*)            CANMSG11_BASE)
+#define CANMSG12                    ((CANMSG_Type*)            CANMSG12_BASE)
+#define CANMSG13                    ((CANMSG_Type*)            CANMSG13_BASE)
+#define CANMSG14                    ((CANMSG_Type*)            CANMSG14_BASE)
+#define CANMSG15                    ((CANMSG_Type*)            CANMSG15_BASE)
 #define TSN                         ((TSN_Type*)               TSN_BASE)
 #define UID                         ((UID_Type*)               UID_BASE)
 
@@ -3256,6 +3270,16 @@
 #define DBG_DBGSTOPCR_FRZEN0_Pos          (0UL)                     /*!< DBG DBGSTOPCR: FRZEN0 (Bit 0)                         */
 #define DBG_DBGSTOPCR_FRZEN0_Msk          (0x1UL)                   /*!< DBG DBGSTOPCR: FRZEN0 (Bitfield-Mask: 0x01)           */
 
+/* ========================================================  PORT  ========================================================= */
+#define PORT_PIN0       (0x01UL)                    /*!< PIN0 (Bit 0)                     */
+#define PORT_PIN1       (0x02UL)                    /*!< PIN1 (Bit 1)                     */
+#define PORT_PIN2       (0x04UL)                    /*!< PIN2 (Bit 2)                     */
+#define PORT_PIN3       (0x08UL)                    /*!< PIN3 (Bit 3)                     */
+#define PORT_PIN4       (0x10UL)                    /*!< PIN4 (Bit 4)                     */
+#define PORT_PIN5       (0x20UL)                    /*!< PIN5 (Bit 5)                     */
+#define PORT_PIN6       (0x40UL)                    /*!< PIN6 (Bit 6)                     */
+#define PORT_PIN7       (0x80UL)                    /*!< PIN7 (Bit 7)                     */
+
 
 /* =========================================================================================================================== */
 /* ================                                            CAN                                            ================ */
